This invention relates to differential signaling drivers, and more particularly pseudo-emitter-coupled logic (PECL) drivers.
Full-voltage-swing signaling has been used to reduce power in circuits. A complementary metal-oxide-semiconductor (CMOS) output can swing from ground to the power-supply voltage, such as 0-5 or 0-3 volts. However, as signal speeds increase, unwanted electro-magnetic interference (EMI) is increasingly generated, and signal quality deteriorates due to reflections, ringing, and voltage undershoot.
Reducing the voltage swing reduces these undesirable effects. However, noise margin is also reduced as the voltage swing is cut. Noise margin can be improved by using two signal wires to transmit a logical signal, rather than just one wire. Such differential signaling has been used for many years in bipolar emitter-coupled logic (ECL) systems.
More recently, the benefits of differential ECL signaling and low-power CMOS have been combined in what is known as pseudo-emitter-coupled logic (PECL). PECL uses differential signaling and current-steering through CMOS transistors. Data rates as high as 1 Giga-bit per second are desired.
FIG. 1A shows a differential signaling scheme. Driver 10 drives lines Y1, Y2 with opposite data. Current is steered among lines Y1, Y2 so that the amount of current passing through each of resistors 14 varies with the data. The I*R voltage drop across resistors 14 can be sensed by receiver 12. The other terminal of resistors 14 is connected to terminating voltage VTT.
FIG. 1B highlights the small voltage swing of differential signaling. Lines Y1, Y2 are driven to opposite states, depending on the data transmitted. The logic high level is reached when Y1 is driven to a VOH voltage, while the complement line Y2 is driven to a VOL level. For the logic low level, Y1 is driven to the VOL voltage, while the complement line Y2 is driven high to a VOH level.
To minimize EMI radiation and signal distortion, VOH and VOL are chosen to be close to each other. This minimizes the voltage swing from VOL to VOH. For example, VOL can be set to 1.66 volts, while VOH is set to 2.33 volts in systems with 3-volt supplies. The signal swing is thus reduced to about 700 mV. The terminating voltage VTT can be set to 2 volts below Vcc, or about 1.3 volts. This is below both VOH and VOL.
When 50-ohm terminating resistors are used for lines Y1, Y2, the amount of current to produce the desired VOH and VOL levels can be calculated using Ohm""s law. The current switched is I=V/R=0.33v/50=6.6 mA.
The parent application, now U.S. Pat. No. 6,429,217, described a current-boosting differential amplifier. A pulse generator is used to pulse on a boost current during switching. This boost current allows the outputs to more quickly reach the desired voltage levels. Once the boost ends, current is reduced, saving power.
While useful, another variation that more closely integrates differential pre-buffering with the pulse generator is desired. A current-boosting differential amplifier that switches currents is desired. A PECL driver with low-voltage swing is desirable. A high-switching speed differential driver with low standby power is desired.